Method for controlling interrupts and auxiliary control circuit

ABSTRACT

An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

FIELD OF THE INVENTION

[0001] This present invention relates generally to microprocessorsystems, and, more particularly, to a method and an auxiliary circuitfor controlling interrupts.

BACKGROUND OF THE INVENTION

[0002] While a microprocessor is working, it may be necessary tointerrupt the program it is running to execute certain instructions.This is done by using flag signals called interrupts or interruptrequests. An interrupt controller receives these flag signals fromperipherals and, depending on the received interrupt, sends to theprocessor an interrupt command and an interrupt pointer vector. Thepointer vector specifies a memory location at which a relative interruptservice routine (ISR) to be run is stored.

[0003] The microprocessor then suspends the operation in progress, savesthe state of the program being run so that it may resume the programlater, and carries out the instructions of the ISR routine relative tothe received interrupt. When the ISR routine has been performed, theprocessor restores the state of the program and, if no other interruptis pending, resumes the program from the point at which it wasinterrupted.

[0004] Interrupt controllers typically have priority registers forestablishing which interrupt, among a plurality of received interruptsthat are pending, are to be served first. A basic prior art interruptcontrol circuit or controller with priority ratings is illustrated inFIG. 1. The interrupt flags, INTO, . . . , INTk, which are generated byperipherals, are stored in a pending interrupt register INT PENDING REG.

[0005] The block IRQ MASK AND PRIORITY LOGIC includes a so-called maskof interrupts and a priority logic circuit. The priority logic circuitgenerates an interrupt request signal IRQ REQ and stores its relativepriority HIGHEST PRIORITY INT in the register CURR IRQ PRIORITY REG.

[0006] A circuit HIGHEST PRIORITY INT (illustrated with a dashed box) isfor processing interrupt request signals based upon the prioritythereof. Its core is a state machine IRQ SM which receives as an inputan interrupt request signal, and it generates an interrupt command nIRQfor the microprocessor. The interrupt request signal IRQ REQ selects aninterrupt vector IRQ VECTOR corresponding to the interrupt to be served,which is read from an interrupt table IRQ VECTOR REG that storesinterrupt vectors identifying corresponding ISR routines.

[0007] The register CURR IRQ PRIORITY REG and the register INT PRIORITYSTACK allow so-called nested interrupts. The register CURR IRQ PRIORITYREG stores the priority of the currently served interrupt. If aninterrupt with a higher priority rating is generated, servicing of thefirst interrupt is suspended and the relative priority is stored in theregister INT PRIORITY STACK, while the new interrupt of higher priorityis served and its priority is stored in the register CURR IRQ PRIORITYREG.

[0008] Once the second interrupt of higher priority has been served, thepreviously suspended interrupt is resumed, if it has a higher prioritythan any other pending interrupts. Once it has been served, it isdeleted from the stack INT PRIORITY STACK by a command STACK PUSH/POP ofthe state machine IRQ SM.

[0009] The interrupt control circuit has a limited number of input pinsdedicated for receiving interrupts from peripherals. Therefore, asillustrated in FIG. 2, only a few peripherals can avail themselves ofthe dedicated input pins of the interrupt control circuit, while otherperipherals share a common input pin for all their interrupts.

[0010] As shown in FIG. 3, the peripheral A is connected to theinterrupt control circuit INTERRUPT CONTROLLER such that each possibleinterrupt signal corresponds to a dedicated pin of the control circuit.By contrast, the peripheral B may use only one pin of the interruptcontrol circuit INTERRUPT CONTROLLER for all of its interrupts.

[0011] For peripheral B, the interrupt control circuit receives aninterrupt signal IRQm that is obtained by ORing the interrupts stored inthe interrupt pending register of the peripheral. When the signal IRQmis active, the interrupt control circuit sends to the microprocessor aninterrupt command nIRQ and an interrupt vector IRQVECTOR identifying aspecific interrupt service routine ISR. This results in the reading ofthe interrupt pending register of the peripheral B for identifying therequested interrupt, and the eventual serving thereof. Of course, thisburdens the processor in executing the ISR routine because it has toread the interrupt pending register of the peripheral B before servingthe interrupt.

SUMMARY OF THE INVENTION

[0012] In accordance with the present invention, a method is providedfor controlling interrupts which allows the microprocessor to quicklyknow which interrupt is to be served, even if the control circuitreceives an interrupt signal resulting from ORing different interruptflags.

[0013] The method of the invention includes generating a bit stringwhich identifies the position of an active bit in the interrupt pendingregister of the peripheral requesting the interrupt, and sending thebit-string to the processor. In this way, the processor is able tosubstantially immediately recognize which interrupt of the peripheral isto be served or processed without having to read the interrupt pendingregister of the peripheral.

[0014] More particularly, a method for controlling interrupts generatedby a peripheral in accordance with the present invention may includestoring, in an interrupt pending register, active bits corresponding tointerrupt flags generated by the peripheral. Further, an interruptsignal resulting from ORing the interrupt flags may be sent to aninterrupt control circuit coupled to the peripheral. When the interruptcontrol circuit receives the interrupt signal, the interrupt signal maybe identified and served.

[0015] In accordance with the invention, identification of the interruptto be served is significantly less burdensome on the processor thatexecutes the corresponding routine. This is done by generating in theperipheral a bit string identifying, by a corresponding active bit ofthe string, the interrupt to be served, and sending this bit string to aprocessor that will so recognize the interrupt based thereon andeventually serve it by executing the corresponding routine.

[0016] The above-described method may be implemented by an auxiliarycontrol circuit that includes an encoding circuit for encoding in a bitstring the position of an active bit stored in the interrupt pendingregister of the peripheral that generated an interrupt flag. Theauxiliary control circuit may then send the bit string to the processor.By way of example, the auxiliary control circuit may be implemented in adedicated device to which a plurality of peripherals are coupled, or itmay be implemented in each one of the peripherals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The various aspects and advantages of the present invention willbecome more apparent through a detailed description thereof, withreference to the accompanying drawings, in which:

[0018]FIG. 1 is schematic circuit diagram of a basic prior art interruptcontrol circuit;

[0019]FIG. 2 is a schematic circuit diagram of a prior artmicroprocessor system in which certain peripherals send interrupts tothe microprocessor via dedicated pins of the control circuit, while theinterrupts of other peripherals share a single pin;

[0020]FIG. 3 is a schematic circuit diagram of two interrupt pendingregisters connected in different ways to an interrupt control circuit inaccordance with the prior art;

[0021]FIG. 4 is a schematic circuit diagram illustrating a firstembodiment of an auxiliary interrupt control circuit in accordance withthe present invention connected to a plurality of peripherals;

[0022]FIG. 5 is a schematic circuit diagram illustrating a secondembodiment of an auxiliary interrupt control circuit in accordance withthe present invention including interrupt mask circuits;

[0023]FIG. 6 is a schematic circuit diagram illustrating anotherembodiment of an auxiliary interrupt control circuit in accordance withthe present invention including a RAM for defining the priority levelsof interrupts;

[0024]FIG. 7 is a schematic circuit diagram illustrating amicroprocessor system including an auxiliary interrupt control circuitin accordance with the present invention; and

[0025]FIG. 8 is a schematic circuit diagram of a peripheral including anauxiliary interrupt control circuit in accordance with the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Referring now to FIG. 4, a first embodiment of the auxiliaryinterrupt control circuit AUXILIARY IC in accordance with the presentinvention is first described. This circuit may be implemented as adevice distinct from the peripherals and from the interrupt controlcircuit INTERRUPT CONTROLLER, and it is connected to a plurality ofperipherals through the bus DATA BUS as shown.

[0027] The auxiliary circuit AUXILIARY IC includes an encoding circuitENCODER that generates a bit string. The bit string identifies theposition of an active bit stored in the interrupt pending register ofthe peripheral that required the interrupt, and it corresponds to theinterrupt to be served. This bit string is sent to the microprocessorCPU which knows substantially immediately which interrupt is to beserved based thereon. This is so even if the control circuit received aninterrupt signal resulting from ORing different interrupt flags.Therefore, the processor need not read the contents of the interruptpending register of the peripheral that has requested the interrupt.Instead, it may serve it directly.

[0028] The auxiliary circuit AUXILIARY IC has an auxiliary register TEMPINT PENDING REG for use in the encoding operation. When an interrupt IRQis received by the interrupt control circuit, the microprocessor CPUidentifies the peripheral it belongs to and copies the entire contentsof the relative interrupt pending register PERIPHERAL INT PENDING REG inthe auxiliary register TEMP INT PENDING REG.

[0029] The encoding circuit ENCODER generates a bit string thatidentifies the position of a first active bit stored in the auxiliaryregister and sends it to the microprocessor through the register FIRSTONE REG and the bus DATA BUS. In the illustrated example, the connectedperipherals have 32-bit registers for storing pending interrupts, thus a5-bit string is sufficient for encoding the position of the first activebit.

[0030] Optionally, the encoding circuit ENCODER may also generate asecond bit string for encoding the last active bit stored in theauxiliary register, and even a third bit string for encoding the numberof active bits stored therein. These last two strings are stored inrespective dedicated registers LAST ONE REG and NUMBER OF ONES REG,before being sent to the microprocessor.

[0031] As illustrated in FIG. 5, the auxiliary circuit of the presentinvention may have priority interrupt masks INT MASK and INT PRIORITYMASK, respectively. Here, the first active bit identified by the stringgenerated by the encoding circuit ENCODER corresponds to the interruptwith highest priority. For example, assuming that the auxiliary registerstores the following string:

[0032] 0001 0010 0011 1100 1000 1000 0000 0000,

[0033] and the priority interrupt mask(s) assigns a higher priority tothe bits from the ninth to the twentieth than to the other bits, theencoding circuit ENCODER will identify the eleventh bit with the firststring, because it is the first active bit having the highest priority.

[0034] In the case where the auxiliary register stores the followingstring:

[0035] 0001 0010 0000 0000 0000 1000 0000 0000,

[0036] and the priority interrupt mask(s) is the same as in the previousexample, the first string of the circuit ENCODER will identify thefourth bit.

[0037] According to another embodiment illustrated in FIG. 6, theauxiliary interrupt control circuit of the present inventionillustratively includes a writable memory RAM PRIORITY MASK that storespriority values for configuring, from time to time, the priorityinterrupt mask(s). It is generally desirable to embody the auxiliarycircuit of the present invention in the interrupt control circuit. Thisallows the same memory that is already present in a common interruptcontrol circuit INTERRUPT CONTROLLER to be shared for the samefunctions. This is particularly convenient given that the memory of theinterrupt control circuit that stores priority values is periodicallyupdated. Having a memory RAM PRIORITY MASK in the auxiliary controlcircuit as well would require a duplication of the updating.

[0038] The auxiliary interrupt control circuit AUXILIARY IC inaccordance with the present invention may be implemented as a separatedevice that is coupled to a plurality of peripherals, as illustrated inFIG. 7. It may also be incorporated in a respective peripheral forproviding to the interrupt control circuit an interrupt signalcorresponding to the logic OR of different interrupt flags. Thisembodiment is illustrated in FIG. 8. Here, the peripheral illustrativelyincludes the interrupt pending register INT PENDING REG and theperipheral circuits PERIPHERAL KERNEL. The block PERIPHERAL KERNELgenerates the interrupts flags INTO, . . . , INTn that are stored in theinterrupt pending register INT PENDING REG, while an OR gate generatesthe interrupt signal IRQm that is provided to the control circuitINTERRUPT CONTROLLER by ORing the various interrupt flags.

[0039] The auxiliary control circuit reads the interrupt pendingregister and generates, at a minimum, a code that identifies a firstactive bit in the register INT PENDING REG and sends it to the processorthrough the bus DATA BUS. Optionally, the auxiliary circuit embodied inthe peripheral may also include a priority mask(s) as discussed abovewith reference to FIG. 5.

That which is claimed is:
 1. A method of controlling interruptsgenerated by a peripheral, comprising: storing, in an interrupt pendingregister, active bits corresponding to interrupt flags generated by saidperipheral; sending to an interrupt control circuit coupled to saidperipheral an interrupt signal obtained by ORing said interrupt flags;upon receiving said interrupt signal said interrupt control circuit,identifying and serving the interrupt; characterized in that it furthercomprises generating a respective bit string identifying an active bitcorresponding to the interrupt that must be served; and serving theinterrupt corresponding to said bit string.
 2. The method of claim 1,wherein said bit string identifies the position of the first active bitin said interrupt pending register of the peripheral that requested theinterrupt.
 3. The method of claim 1, comprising the step of generating asecond bit string identifying the position of the last active bit insaid interrupt pending register of the peripheral that requested theinterrupt.
 4. The method of claim 1, comprising the step of generating athird bit string identifying the number of active bits in said interruptpending register of the peripheral that requested the interrupt.
 5. Themethod of claim 1, comprising the steps of: once the peripheral thatgenerated the relative interrupt flag has been identified, copying thecontent of the interrupt pending register of the peripheral in anauxiliary register; and generating said bit string in function of thecontent of said auxiliary register.
 6. An auxiliary interrupt controlcircuit, connectable to an interrupt control circuit, to amicroprocessor and to at least a peripheral having an interrupt pendingregister, said control circuit receiving an interrupt signalcorresponding to the logic OR of interrupt flags stored in saidinterrupt pending register, said auxiliary circuit comprising: anencoding circuit coupled to said interrupt pending register of theperipheral, sending to said microprocessor a bit string encoding theposition of an active bit stored in said interrupt pending registercorresponding to a certain interrupt to be served.
 7. The auxiliarycircuit of claim 6, further comprising: an auxiliary register, the sizeof which coincides to that of the interrupt pending register of theconnected peripheral, for storing the content of said interrupt pendingregister; said encoding circuit being coupled to said auxiliary registerand said bit string encoding the position of an active bit stored insaid auxiliary register.
 8. The auxiliary circuit of claim 6, comprisinga first register in which to store said bit string encoding the positionof the first active bit in said interrupt pending register.
 9. Theauxiliary circuit of claim 6, comprising a second register in which tostore a second bit string encoding the position of a last active bit insaid interrupt pending register.
 10. The auxiliary circuit of claim 6,comprising a third register in which to store a third bit stringgenerated by said encoding circuit (ENCODER) encoding the number ofactive bits in said interrupt pending register.
 11. The auxiliarycircuit of claim 6, further comprising an interrupt priority maskcircuit, said first bit string encoding the position of an active bitcorresponding to a pending interrupt of highest priority.
 12. Theauxiliary circuit of claim 11, further comprising a writable memorystoring the priority values provided by said interrupt control circuitstored, said interrupt priority mask circuit depending on whichperipheral generated an interrupt being configured in function ofrespective priority values stored in said writable memory.
 13. Aperipheral connectable to a microprocessor and to an interrupt controlcircuit, associated to an interrupt pending register, said interruptcontrol circuit receiving an interrupt signal corresponding to the logicOR of interrupt flags generated by the peripheral and stored in saidinterrupt pending register, characterized in that it comprises anauxiliary control circuit as defined in claim
 6. 14. A microprocessorsystem, comprising an interrupt control circuit, a plurality ofperipherals each being associated to a respective interrupt pendingregister, said control circuit receiving respective interrupt signalscorresponding to the logic OR of interrupt flags stored in therespective interrupt pending register, a microprocessor coupled to saidcontrol circuit and to said peripherals, characterized in that itcomprises: an auxiliary control circuit as defined in claim 6 coupled tosaid peripherals and sending to said microprocessor a bit stringencoding the position of an active bit stored in the interrupt pendingregister of the peripheral that generated the interrupt.